1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a wordline driver for a flash Electrically Erasable Programmable Read-Only Memory (EEPROM).
2. Description of the Related Art
A microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting select transistors which would enable the cells to be erased independently. All of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block.
The cells are connected in a rectangular array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying, typically, 9 V to the control gate, 5 V to the drain and grounding the source, which causes hot electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein which increases the threshold voltage of the cell to a value in excess of approximately 4 V.
The cell is read by applying typically 5 V to the control gate, 1 V to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 V), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 V), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, a cell is erased by applying typically 12 V to the source, grounding the control gate and allowing the drain to float. This causes the electrons which were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Alternatively, a cell can be erased by applying a negative voltage on the order of -10 V to the control gate, applying 5 V to the source and allowing the drain to float.
Power supply voltages for flash EEPROMs are being reduced together with the reduction in feature sizes. A supply voltage of 5 V has been standard in the industry for some time. However, with feature sizes being reduced to values on the order of 0.35 and 0.25 microns, power supply voltages have been reduced to 3 V or less to prevent application of excessive voltages to the smaller cell elements.
A memory cell is conventionally read by applying the positive power supply voltage V.sub.cc (conventionally 5 V) to the gate of the cell via the corresponding wordline. However, with smaller cells and supply voltages of 3 V or less, a problem has been encountered in that application of V.sub.cc to the gate does not produce enough cell current to ensure a reliable read operation.
A partial solution to this problem is to provide a booster circuit which boosts the wordline read pulse voltage (cell gate voltage) to a value higher than V.sub.cc, thereby increasing the read current. A prior art booster circuit 2 is illustrated in FIG. 1. A boost capacitor CB is connected in series with a PMOS transistor T1 between the supply voltage V.sub.cc and a wordline WL. The load capacitance of the wordline WL is represented by a capacitance CL which appears between the wordline WL and ground.
Another PMOS, transistor T2 is connected between V.sub.cc and the wordline WL. A logic circuit 4 has an output connected to the gate of the transistor T2 and an input connected to receive an Address Transition Detector (ATD) signal. The ATD signal is also applied to another logic circuit 6 which has an output connected to the gate of the transistor T1.
The ATD signal is a pulse which is generated for a certain length of time, typically 10 ns, in response to a detection of a change of logical state on an input address pin. The change can be from logical "1" to logical "0" or vice-versa. With reference also being made to FIG. 2, in response to the ATD pulse, the logic circuit 4 applies 0 V to the transistor T2 which turns it on and connects the wordline WL to the supply voltage V.sub.cc. During this period the logic circuit 6 turns off the transistor T1 and disconnects the boost capacitor CB from V.sub.cc. Thus, V.sub.cc is applied to the wordline WL, and the wordline voltage V.sub.WL =V.sub.cc. This operation pre-charges the wordline WL.
At the termination of the ATD pulse, the logic circuit 4 turns off the transistor T2 to disconnect the wordline WL from V.sub.cc. The logic circuit 6 turns on the transistor T1 to connect the boost capacitor CB to V.sub.cc. A voltage BOOST.sub.-- CLK which appears across the capacitor CB (at the source of the transistor T1) is referred to as a "kick" signal or voltage, and causes the wordline capacitance CL to charge in accordance with the capacitor divider effect. The wordline voltage V.sub.WL increases to a value VH which is higher than V.sub.cc, typically 4 to 5 V for V.sub.cc =3 V.
The wordline voltage V.sub.WL is thereby boosted above the supply voltage V.sub.cc for the duration of the read pulse, causing sufficient current to flow through a memory cell connected to the wordline WL to ensure a reliable read operation. However, a problem has existed in this prior art booster circuit 2 in that the boosted voltage VH varies with V.sub.cc which itself can vary due to temperature and other conditions. If the boosted read voltage becomes too high, it can create a condition known as "gate disturb" in which cells on the same wordline as the cell that is being read will have undesired electrons and thereby negative charge transferred to its floating gate due to the high control gate voltage. In an extreme case, this can cause an erased cell to become programmed.